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? ds6255a/b-02 march 2017 www.richtek.com 1 ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. rt6255a/b 5a, 18v, 500khz, acot tm step-down converter features ? ? ? ? ? input supply voltage range : 4.5v to 18v ? ? ? ? ? output current : 5a ? ? ? ? ? advanced constant on-time (acot tm ) control for ultrafast transient response ? ? ? ? ? steady switching frequency : 500khz ? ? ? ? ? forced pwm mode (rt6255b) ? ? ? ? ? pulse-skipping mode (psm) at light load (rt6255a) ? ? ? ? ? optimized for low-esr ceramic output capacitors ? ? ? ? ? programmable output voltage : 0.6v to 5v ? ? ? ? ? internal 45m switch and 23m synchronous rectifier ? ? ? ? ? cycle-by-cycle current limit protection ? ? ? ? ? internal soft-start (typ 1.5ms) or externally adjustable, pre-biased compatible soft-start (only for option with ss pin) ? ? ? ? ? power good indicator (90%) (only for option with pgood pin) ? ? ? ? ? output under-voltage protection (uvp) ? ? ? ? ? over-temperature protection (otp) ? ? ? ? ? input under-voltage lockout (uvlo) ? ? ? ? ? available in tsot-23-6 (fc) and tsot-23-8 (fc) packages applications ? set top box ? portable tv ? access point router ? dsl modem ? lcd tv note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. ordering information general description the rt6255a/b is a high-efficiency, synchronous step- down dc-dc converter that can deliver up to 5a output current from a 4.5v to 18v input supply. the rt6255a/b adopts advanced constant on-time (acot tm ) control architecture to provide an ultrafast transient response with few external components and to operate in nearly constant switching frequency over line, load, and output voltage ranges. the rt6255a/b features cycle-by-cycle current limit protection against short-circuit outputs, and soft-start function to prevent inrush current during start-up. it also includes input under-voltage lockout, output under-voltage protection, and over-temperature protection (thermal shutdown) to provide safe and smooth operation in all operating conditions. rt6255a/b package type j6f : tsot-23-6 (fc) j8f : tsot-23-8 (fc) lead plating system g : green (halogen free and pb free) uvp option h : hiccup psm/pwm a : psm/pwm b : force-pwm ( ) pin8 definition empty means pgood pin s : ss pin
rt6255a/b 2 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin configuration (top view) tsot-23-6 (fc) tsot-23-8 (fc) fb en gnd boot lx vin 4 23 5 6 marking information 27=dnn 27= : product code dnn : date code rt6255ahgj6f rt6255bhgj6f 26=dnn 26= : product code dnn : date code rt6255ahgj8f 1c=dnn 1c= : product code dnn : date code 1b=dnn rt6255bhgj8f 1b= : product code dnn : date code rt6255ahsgj8f 1u=dnn 1u= : product code dnn : date code rt6255bhsgj8f 1t=dnn 1t= : product code dnn : date code fb agnd gnd pgood/ss lx vin en boot 5 34 6 8 2 7 pin no. pin name pin function tsot-23-6 (fc) tsot-23-8 (fc) 1 1 fb feedback voltage input. this pin is used to set the desired output voltage via an external resistive divider. -- 3 agnd analog ground. this is the signal ground reference for the ic. 2 2 en enable control input. connecting this pin to logic high can enable the device and connecting this pin to gnd can disable the device. 3 4 gnd system ground. this is the power return for the ic. 4 5 vin power input. supplies the power switches of the device. functional pin description
rt6255a/b 3 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin no. pin name pin function tsot-23-6 (fc) tsot-23-8 (fc) 5 6 lx switch node. lx is the switching node that supplies power to the output and connect the output lc filter from lx to the output load. 6 7 boot bootstrap supply for high-side gate driver. connect a 0.1 ? f ceramic capacitor from lx to boot to power the high-side switch. -- 8 pgood power good indicator. open-drain output when the output voltage is within 90% to 120% of regulation point. -- 8 ss soft-start control input. connect a capacitor from ss to gnd to set the soft-start time. the capacitance c ss is suggested to be in the range from 2.8nf to 220nf. functional block diagram (rt6255ahgj6f/rt6255bhgj6f) ugate lgate driver lx boot p vcc control on-time en comparator lx gnd reg vibias v ref p vcc + - lx ripple gen. vin fb minoff en vin gnd lx vin uv oc + v cc v cc
rt6255a/b 4 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. (rt6255ahgj8f/rt6255bhgj8f) (rt6255ahsgj8f/rt6255bhsgj8f) ugate lgate driver lx boot p vcc control on-time en comparator lx gnd reg vibias v ref p vcc + - lx ripple gen. vin fb minoff en vin gnd lx vin uv oc pgood agnd + v cc v cc ugate lgate driver lx boot p vcc control on-time en comparator lx gnd reg vibias v ref p vcc + - lx ripple gen. vin fb minoff en vin gnd lx vin uv oc agnd + v cc ss v cc
rt6255a/b 5 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation the rt6255a/b is a high-efficiency, monolithic synchronous ste p-down dc-dc converter that can deliver up to 5a output current from a 4.5v to 18v input supply. using the acot control mode can reduce the output capacitance and perform fast transient response. it can minimize the component size without additional external compensation network. current limit the rt6255a/b current limit is a cycle-by-cycle ? valley ? type, measuring the inductor current through the synchronous rectifier during the off-time while the inductor current ramps down. the current is determined by measuring the voltage between source and drain of the synchronous rectifier, adding temperature compensation for greater accuracy. if the current exceeds the current limit, the on-time one-shot is inhibited until it drops below the current limit level. if the output current exceeds the available inductor current (controlled by the current limit mechanism), the output voltage will drop. if it drops below the output under-voltage protection level (see next section) the ic will stop switching to avoid excessive heat. hiccup mode the rt6255a/b use hiccup mode for uvp. when the protection function is triggered, the ic will shut down for a period of time and then attempt to recover automatically. hiccup mode allows the circuit to operate safely with low input current and power dissipation, and then resume normal operation as soon as the overload or short circuit is removed. input under-voltage lockout to protect the chip from operating at insufficient supply voltage, the uvlo is needed. when the input voltage of v in is lower than the uvlo falling threshold voltage, the device will be lockout. shut-down, start-up and enable (en) the enable input (en) has a logic-low level. when v en is below this level the ic enters shutdown mode. when v en exceeds its logic-high level the ic is fully operational. external bootstrap capacitor connect a 0.1 f low esr ceramic capacitor between boot and lx. this bootstrap capacitor provides the gate driver supply voltage for the high side n- mosfet switch. over-temperature protection the rt6255a/b includes an over-temperature protection (otp) circuitry to prevent overheating due to excessive power dissipation. the otp will shut down switching operation when the junction temperature exceeds 150 c. once the junction temperature cools down by approximately 15 c, the ic will resume normal operation. for continuous operation, provide adequate cooling so that the junction temperature does not exceed 150 c. uvp protection the rt6255a/b detects under-voltage conditions by monitoring the feedback voltage on fb pin. when the feedback voltage is lower than 60% of the target voltage, the uvp comparator will go high to turn off both internal high-side and low-side mosfets. soft-start (ss) (for rt6255ahsgj8f/rt6255bhsgj8f) the soft-start function is used to prevent large inrush currents while the converter is being powered up. the rt6255a/b provides a soft-start feature for inrush control. for some options, it provides an ss pin so that the soft- start time can be programmed by selecting the value of the external capacitor c ss connected from the ss pin to gnd. during the start-up sequence, the external capacitor is charged by an internal current source i ss (typically, 4 a) to generate a soft-start ramp voltage as a reference voltage to the pwm comparator. the device will initiate switching and the output voltage will smoothly ramp up to its targeted regulation voltage only after this ramp voltage is greater than the feedback voltage v fb to ensure the converters have a smooth start-up. for soft-start control, the ss pin should never be left unconnected.
rt6255a/b 6 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power good indicator (for rt6255ahgj8f/rt6255bhgj8f) the pgood pin is an open-drain output and is connected to an external pull-up resistor. it is controlled by a comparator, which the feedback signal v fb is fed to. if v fb is above 90% of the internal reference voltage, the pgood pin will be in high impedance and v pgood will be held high. otherwise, the pgood output will be pulled low.
rt6255a/b 7 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics (v in = 12v, t a = 25c, unless otherwise specified) absolute maximum ratings (note 1) ? supply input voltage, vin ------------------------------------------------------------------------------------------- ? 0.3v to 20v ? enable pin voltage, en ---------------------------------------------------------------------------------------------- ? 0.3v to 20v ? switch node v oltage, lx --------------------------------------------------------------------------------------------- ? 0.3v to 20v <20ns -------------------------------------------------------------------------------------------------------------------- ? 5v to 27v ? boot to lx, v boot ? v lx -------------------------------------------------------------------------------------------- ? 0.3v to 6v ? other pins --------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v ? power dissipation, p d @ t a = 25 c tsot -23-6 (fc) -------------------------------------------------------------------------------------------------------- 1.923w tsot -23-8 (fc) -------------------------------------------------------------------------------------------------------- 1.923w ? package thermal resistance (note 2) tsot-23-6 (fc), ja --------------------------------------------------------------------------------------------------- 52 c/w tsot-23-6 (fc), jc ------------------------------------------------------------------------------------------------------------------------------- -------------- 5 c/w tsot-23-8 (fc), ja --------------------------------------------------------------------------------------------------- 52 c/w tsot-23-8 (fc), jc -------------------------------------------------------------------------------------------------- 5 c/w ? junction te mperature ------------------------------------------------------------------------------------------------- 150 c ? lead temperature (soldering, 10 se c.) --------------------------------------------------------------------------- 260 c ? storage temperature range ----------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (huma n body model) ----------------------------------------------------------------------------------------- 2kv recommended operating conditions (note 4) ? supply input voltage -------------------------------------------------------------------------------------------------- 4.5v to 1 8v ? junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 125 c ? ambient temperature range ---------------------------------------------------------------------------------------- ? 40 c to 85 c parameter symbol test conditions min typ max unit supply voltage vin supply input operating voltage v in 4.5 -- 18 v vin under-voltage lockout threshold-rising v uvlo v in rising 3.9 4.1 4.3 v vin under-voltage lockout threshold-hysteresis ? v uvlo -- 0.3 -- v supply current supply current (shutdown) i shdn v en = 0 -- 3 -- ? a supply current (quiescent) i q i out = 0 v fb = v ref x 105% (not switching) -- 115 -- ? a soft-start soft-start time t ss -- 1.5 -- ms
rt6255a/b 8 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a four-layer richtek evaluation board. jc is measured at the lead of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit enable voltage en input high voltage v en_h 1.5 -- -- v en input low voltage v en_l -- -- 0.4 v feedback voltage feedback threshold voltage v th _ fb 0.594 0.6 0.606 v feedback current i fb v fb = 4v ? 50 -- 50 na internal mosfet high-side switch on-resistance r ds(on)_h v boot ? v lx = 4.8v -- 45 -- m ? low-side switch on-resistance r ds(on)_l -- 23 -- m ? discharge fet r on r dischg -- 50 -- ? current limit hide-side switch current limit i lim_h -- 10.5 -- a low-side switch valley current limit i lim_l 5.25 7.25 9.25 a switching frequency oscillator frequency f sw 400 500 600 khz on-time timer control minimum on-time t on_min v in = v in(max) -- 60 -- ns minimum off-time t off_min -- 200 -- ns thermal shutdown thermal shutdown threshold t sd -- 150 -- ? c thermal shutdown hysteresis ? t sd -- 15 -- ? c output under voltage uvp trip threshold uvp detect -- 60 -- % hysteresis -- 10 -- % power good for (rt6255ahgj8f/rt6255bhgj8f) power good threshold v pgood v fb rising 85 90 95 % v fb falling 80 85 90 % ss for (rt6255ahsgj8f/rt6255bhsgj8f) soft-start current i ss -- 4 -- ? a
rt6255a/b 9 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit note 1 : all the input and output capacitors are the suggested values, referring to the effective capacitances, subject to any de-rating effect, like a dc bias. note 2 : considering the noise immunity, it is necessary to add r t = 4.99k between feedback network and chip fb pin. table 1. suggested component values v out (v) r1 (k ? ) r2 (k ? ) l ( ? h) c out ( ? f) c ff (pf) 1 13.3 20 1.5 44 -- 1.2 20 20 1.5 44 -- 1.8 40.2 20 2 44 -- 2.5 63.4 20 2.8 44 47 to 82 3.3 90.9 20 3.3 44 47 to 82 5 147 20 4.7 44 47 to 82 * : pgood pin is for (rt6255ahgj8f/rt6255bhgj8f) rt6255a/b en vin boot pgood* 22f lx 0.1f 1.5h v out 1v gnd v in 4.5v to 18v c1 c2 22f c boot fb r1 r2 c ff option 13.3k 20k enable agnd r pgood 100k v pgood c3 22f l 5k r t * : ss pin is for (rt6255ahsgj8f/rt6255bhsgj8f) rt6255a/b en vin boot ss* 22f lx 0.1f 1h v out 1v gnd v in 4.5v to 18v c1 c2 22f c boot fb r1 r2 c ff option 13.3k 20k enable agnd c ss 3.9nf c3 22f l 5k r t
rt6255a/b 10 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) v out = 1v, l = 1.5 h v in = 4.5v v in = 5v v in = 12v v in = 18v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) v out = 3.3v, l = 4.7 h v in = 4.5v v in = 5v v in = 12v v in = 18v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 output current (a) efficiency (%) v out = 5v, l = 4.7 h v in = 7v v in = 12v v in = 18v output voltage vs. output current 0.90 0.95 1.00 1.05 1.10 00.511.522.533.544.55 output current (a) output voltage (v) v out = 1v v in = 18v v in = 12v v in = 4.5v output current vs. output current 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 5.30 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 output current (a) output voltage (v) v out = 5v v in = 18v v in = 12v v in = 7v en threshold vs. temperature 1.10 1.15 1.20 1.25 1.30 1.35 -50 -25 0 25 50 75 100 125 temperature (c) en threshold(v) rising v out = 1v falling
rt6255a/b 11 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (2 s/div) output ripple voltage v out (20mv/div) v lx (5v/div) v in = 12v, v out = 1v, i out = 5a, l = 1.5 h, c out = 22 f x2 time (10ms/div) power on from en v out (1v/div) v lx (10v/div) v in = 12v, v out = 1v, i out = 5a v en (2v/div) i out (2a/div) output voltage vs. temperature 0.99 1.00 1.01 1.02 1.03 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 18v v in = 12v v in = 4.5v v out = 1v, i out = ccm output voltage vs. temperature 4.90 4.95 5.00 5.05 5.10 5.15 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 18v v in = 12v v in = 7v v out = 5v, i out = ccm uvlo voltage vs. temperature 3.4 3.6 3.8 4.0 4.2 4.4 4.6 -50 -25 0 25 50 75 100 125 temperature (c) uvlo voltage (v) rising v out = 1v, i out = 0a falling load transient response time (100 s/div) v out (20mv/div) i out (2a/div) v in = 12v, v out = 1v, i out = 0a to 5a, l = 1.5 h, c out = 22 f x 2
rt6255a/b 12 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (10ms/div) power off from vin v out (1v/div) v lx (10v/div) v in = 12v, v out = 1v, i out = 5a v in (10v/div) i out (2a/div) time (10ms/div) power off from en v out (1v/div) v lx (10v/div) v in = 12v, v out = 1v, i out = 5a v en (2v/div) i out (2a/div) time (10ms/div) power on from vin v out (1v/div) v lx (10v/div) v in = 12v, v out = 1v, i out = 5a v in (10v/div) i out (2a/div)
rt6255a/b 13 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information inductor selection the consideration of inductor selection includes inductance, rms current rating and, saturation current rating. the inductance selection is generally flexible and is optimized for the low cost, low physical size, and high system performance. choosing lower inductance to reduce physical size and cost, and it is useful to improve the transient response. however, it causes the higher inductor peak current and output ripple voltage to decrease system efficiency. conversely, higher inductance increase system efficiency, but the physical size of inductor will become larger and transient response will be slow because more transient time is required to change current (up or down) by inductor. a good compromise between size, efficiency, and transient response is to set a inductor ripple current ( i l ) about 20% to 50% of the desired full output load current. calculate the approximate inductance by the input voltage, output voltage, switching frequency (f sw ), maximum rated output current (i out(max) ) and inductor ripple current ( i l ). ? ? ?? ??? out in out in sw l vvv l = vf i once the inductance is chosen, the inductor ripple current ( i l ) and peak inductor current can be calculated. ? ? out in out l in sw l(peak) out(max) l l(vally) out(max) l vvv i= vf l 1 i = i i 2 1 i = i i 2 ?? ? ?? ?? ?? the typical operating ci rcuit design for the rt6255a/b, the output voltage is 1v, maximum rated output current is 5a, input voltage is 12v, and inductor ripple current is 1.5a which is 30% of the maximum rated output current, the calculated inductance value is : ? ? 3 1121 l = = 1.23 h 12 500 10 1.5 ?? ??? the inductor ripple current set at 1.5a and so we select 1.5 h inductance. the actual inductor ripple current and required peak current is shown as below : ? ? l 3-6 1121 i = = 1.23a 12 500 10 1.5 10 ?? ? ???? l(peak) out(max) l 11.23 i = i i = 5 + = 5.615a 22 ?? i nductor saturation current should be chosen over ic's valley current limit. input capacitor selection the effective input capacit ance is a function of the input voltage (v in ), output voltage (v out ), rated output current (i out ), switching frequency (f sw ), and input ripple voltage of the regulator ( v inp ) : out out out in in in(min) sw inp vv i1 vv c = fv ?? ??? ?? ?? ?? ceramic capacitors are most often used because of their low cost, small size, high rms current ratings, and robust surge current capabilities. it should pay attention that value of capacitors change as temperature, bias voltage, and operating frequency change. for example the capacitance value of a capacitor decreases as the dc bias across the capacitor increases. several ceramic capacitors may be paralleled to meet the rms current, size, and height requirem ents of the application. considering the dc bias effects for the input capacitor, the typical operating circuit used two 10 f low esr ceramic capacitors on the vin pin and an additional 0.1 f is recommended to place as close as possible to the ic input side for high frequency filtering. output capacitor selection the rt6255a/b is optimi zed for output terminal with ceramic capacitors application and best performance will be obtained using them. the total output capacitance value is usually determined by the desired output ripple voltage level and transient response requirements for sag which is undershoot on positive load steps and soar which is overshoot on negative load steps.
rt6255a/b 14 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. output ripple voltage output ripple voltage at the switching frequency is caused by the inductor current ripple and its effect on the output capacitor's esr and stored charge. these two ripple components are called esr ripple and capacitive ripple. since ceramic capacitors have extremely low esr and relatively little capacitance, both components are similar in amplitude and both should be considered if ripple is critical. ripple ripple(esr) ripple(c) ripple(esr) l esr l ripple(c) out sw v = v v v = ir i v = 8c f ? ?? ? ?? the typical operating circuit desig n for the rt6255a/b, the output voltage is 1v, inductor ripple current is 1.23a, and using 2 pieces of 22 f output capacitor with about 5m esr, the output voltage ripple components are : ripple(esr) l esr l ripple(c) out sw ripple ripple(esr) ripple(c) v = i r = 1.23a 5m = 6.15mv i 1.23a v = = 8c f 844 f500khz = 6.99mv v = v v = 13.13mv ?? ? ? ? ?? ?? ? output transient undershoot and overshoot in addition to output ripple voltage at the switching frequency, the output capacitor and its esr also affect the voltage sag (undershoot) and soar (overshoot) when the load steps up and down abruptly. the acot tm transient response is very quick and output transients are usually small. however, the combination of small ceramic output capacitors (with little capacitance), low output voltages (with little stored charge in the output capacitors), and low duty cycle applications (which require high inductance to get reasonable ripple currents with high input voltages) increases the size of voltage variations in response to very quick load changes. typically, load changes occur slowly with respect to the ic's 500khz switching frequency. but some modern digital loads can exhibit nearly instantaneous load changes and the following section shows how to calculate the worst-case voltage swings in response to very fast load steps. the output voltage transient undershoot and overshoot each have two components : the voltage steps caused by the output capacitor's esr, and the voltage sag and soar due to the finite output capacitance and the inductor current slew rate. use the following formulas to check if the esr is low enough (typically not a problem with ceramic capacitors) and the output capacitance is large enough to prevent excessive sag and soar on very fast load step edges, with the chosen inductor value. the amplitude of the esr step up or down is a function of the load step and the esr of the output capacitor : esr_step out esr v = ir ?? the amplitude of the capacitive sag is a function of the load step, the output capacitor value, the inductor value, the input-to-output voltage differential, and the maximum duty cycle. the maximum duty cycle during a fast transient is a function of the on-time and the minimum off-time since the acot tm control scheme will ramp the current using on-times spaced apart with minimum off-times, which is as fast as allowed. calculate the approximate on-time (neglecting parasitics) and maximum duty cycle for a given input and output voltage as : out on on max in sw on off_min vt t = and d = vf t t ?? the actual on-time will be slightly longer as the ic compensates for voltage drops in the circuit, but we can neglect both of these since the on-time increase compensates for the voltage losses. calculate the output voltage sag as : ?? 2 out sag out in(min) max out l(i ) v = 2c v d v ?? ?? ?? the amplitude of the capacitive soar is a function of the load step, the output capacitor value, the inductor value and the output voltage : 2 out soar out out l(i ) v = 2c v ?? ??
rt6255a/b 15 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. feedforward capacitor (c ff ) the rt6255a/b is optimized for ceramic output capacitors and for low duty cycle applications. however for high-output voltages, with high feedback attenuation, the circuit's transient response can be slowed. in high-output voltage circuits transient response is improved by adding a small ? feedforward ? capacitor (c ff ) across the upper fb divider resistor (figure 1), to speed up the transient response without affecting the steady-state stability of the circuit. choose a suitable capacitor value that following suggested component bom. figure 1. c ff capacitor setting enable operation (en) for automatic start-up the high-voltage en pin can be connected to vin, through a 100k resistor. its large hysteresis band makes en useful for simple delay and timing circuits. en can be externally pulled to vin by adding a resistor-capacitor delay (r en and c en in figure 2). calculate the delay time using en's internal threshold where switching operation begins. an external mosfet can be added to implement digital control of en when no system voltage above 2v is available (figure 3). in this case, a 100k pull-up resistor, r en , is connected between vin and the en pin. mosfet q1 will be under logic control to pull down the en pin. to prevent enabling circuit when v in is smaller than the v out target value or some other desired voltage level, a resistive voltage divider can be placed between the input voltage and ground and connected to en to create an addition al input under voltage lockout threshold (figure 4). figure 2. external timing control figure 3. digital enable control circuit figure 4. resistor divider for lockout threshold setting rt6255a/b en gnd v in r en c en en rt6255a/b en gnd 100k v in r en q1 enable rt6255a/b en gnd v in r en1 r en2 output voltage setting set the desired output voltage using a resistive divider from the output to ground with the midpoint connected to fb. the output voltage is set according to the following equation : out r1 v0.6v(1 + ) r2 ?? figure 5. output voltage setting rt6255a/b gnd fb r1 r2 v out place the fb resistors within 5mm of the fb pin. choose r2 between 10k and 100k to minimize power consumption without excessive noise pick-up and calculate r1 as follows : out ref ref r2 (v v ) r1 v ?? ? rt6255a/b gnd fb r1 r2 v out c ff
rt6255a/b 16 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. for output voltage accuracy, use divider resistors with 1% or better tolerance. external boot bootstrap diode when the input voltage is lower than 5.5v it is recommended to add an external bootstrap diode between vin and the boot pin to improve enhancement of the internal mosfet switch and improve efficiency. the bootstrap diode can be a low cost one such as 1n4148 or bat54. external boot capacitor series resistance the internal power mosfet switch gate driver is optimized to turn the switch on fast enough for low power loss and good efficiency, but also slow enough to reduce emi. switch turn-on is when most emi occurs since v lx rises rapidly. during switch turn-off, lx is discharged rel atively slowly by the inductor current during the dead time between high-side and low-side switch on-times. in some cases it is desirable to reduce emi further, at the expense of some additional power dissipation. the switch turn-on can be slowed by placing a small (<47 ) resistance between boot and the external bootstrap capacitor. this will slow the high-side switch turn-on and v lx 's rise. to remove the resistor from the capacitor charging path (avoiding poor enhancement due to undercharging the boot capacitor), use the external diode shown in figure 6 to charge the boot capacit or and place the resistance between boot and the capacitor/diode connection. figure 6. external bootstrap diode lx boot 5v 0.1f rt6255a/b thermal considerations the junction temperature should never exceed the absolute maximum junction temperature t j(max) , listed under absolute maximum ratings, to avoid permanent damage to the device. the maximum allowable power dissipation depends on the thermal resistance of the ic package, the pcb layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. the maximum power dissipation can be calculated using the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction-to-ambient thermal resistance. for continuous operation, the maximum operating junction temperature indicated under recommended operating conditions is 125 c. the junction-to-ambient thermal resistance, ja , is highly package dependent. for a tsot-23-6 (fc) package, the thermal resistance, ja , is 52 c/w on a standard jedec 51-7 high effective-thermal- conductivity four-layer test board. for a tsot-23-8 (fc) package, the thermal resistance, ja , is 52 c/w on a standard jedec 51-7 high effective-thermal-conductivity four-layer test board. the maximum power dissipation at t a = 25 c can be calculated as below : p d(max) = (125 c ? 25 c) / (52 c/w) = 1.923w for a tsot-23-6 (fc) package. p d(max) = (125 c ? 25 c) / (52 c/w) = 1.923w for a tsot-23-8 (fc) package. the maximum power dissipation depends on the operating ambient temperature for the fixed t j(max) and the thermal resistance, ja . the derating curves in figure 7 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
rt6255a/b 17 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 7. derating curve of maximum power dissipation 0.0 0.5 1.0 1.5 2.0 2.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb tsot-23-6 (fc) tsot-23-8 (fc) layout considerations follow the pcb layout guidelines for optimal performance of the device. ? keep the traces of the main current paths as short and wide as possible. ? put the input capacitor as close as possible to vin pin. ? lx node is with high frequency voltage swing and should be kept at small area. keep analog components away from the lx node to prevent stray capacitive noise pickup. ? connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the device. ? connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. ? the agnd pin is suggested to connect to 2 nd gnd plate through top to 2 nd via. ? an example of rt6255a/b pcb layout guide is shown in figure 8 and figure 9 for references. fb vin en 4 2 3 5 6 v out r1 r2 c in c in c out keep sensitive components away from this trace. suggestion layout trace wider for thermal. suggestion layout trace wider for thermal. the feedback components must be connected as close to the device as possible. the r en component must be connected to v in . suggestion layout trace wider for thermal. input capacitor must be placed as close to the ic as possible. suggestion layout trace wider for thermal. v out gnd lx boot r en c b l v in lx should be connected to inductor by wide and short trace. keep sensitive components away from this trace. suggestion layout trace wider for thermal. c out figure 8. pcb layout guide for tsot-23-6 package
rt6255a/b 18 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. gnd plate (2nd layer) lx should be connected to inductor by wide and short trace. keep sensit ive components away from this trace. suggestion layout trace wider for thermal. keep sensitive components away from this trace. suggestion layout trace wider for thermal. suggestion layout trace wider for thermal. the feedback components must be connected as close to the device as possible. v out fb agnd gnd pgood lx vin en boot 5 34 6 8 2 7 the agnd is suggested connect to second layer gnd plate by via to get better noise immunity. via c in c in r1 r2 r en gnd plate (top layer) v in the r en component must be connected to v in . suggestion layout trace wider for thermal. input capacitor must be placed as close to the ic as possible. suggestion layout trace wider for thermal. c boot c out c out r pgood via via figure 9. pcb layout guide for tost-23-8 package
rt6255a/b 19 ds6255a/b-02 march 2017 www.richtek.com ? copyright 2017 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. min. max. min. max. a 0.700 1.000 0.028 0.039 a1 0.000 0.100 0.000 0.004 b 1.397 1.803 0.055 0.071 b 0.300 0.559 0.012 0.022 c 2.591 3.000 0.102 0.118 d 2.692 3.099 0.106 0.122 e h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024 symbol dimensions in millimeters dimensions in inches 0.950 0.037 tsot-23-6 (fc) surface mount package outline dimension
rt6255a/b 20 ds6255a/b-02 march 2017 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. tsot-23-8 (fc) surface mount package min. max. min. max. a 0.700 1.000 0.028 0.039 a1 0.000 0.100 0.000 0.004 b 1.397 1.803 0.055 0.071 b 0.220 0.380 0.009 0.015 c 2.591 3.000 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.585 0.715 0.023 0.028 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024 symbol dimensions in millimeters dimensions in inches

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